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Page 1

Digital
 Design
 With
 An
 Introduction
 to
 the
 Verilog
 HDL
 –
 Solution
 Manual.
 M.
 Mano.
 M.D.
 Ciletti,
 Copyright
 2012,
 
 
All
 rights
 reserved.
 

1
 

SOLUTIONS MANUAL

 


 

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+"$,' %*'"*$-.!/0$".*'$.'$,(' 1(-"&.#',!& '

23456'(735389'

 

 

 

 

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<=84>??8='(@>=35A?'

0BC348=93B')5B5>'/93D>=?35EF'&8?'%9G>C>?'

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:"0,%(&'!;'0"&($$" '

<=84>??8='(@>=35A?'
'

/93D>=?35E'84'08C8=B78F'08C8=B78')H=39G?'

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=>D'IJKLMKJILJ '

Page 2

Digital
 Design
 With
 An
 Introduction
 to
 the
 Verilog
 HDL
 –
 Solution
 Manual.
 M.
 Mano.
 M.D.
 Ciletti,
 Copyright
 2012,
 
 
All
 rights
 reserved.
 

2
 


 
CHAPTER 1

1.1 Base-10: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Octal: 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40
Hex: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
Base-12 14 15 16 17 18 19 1A 1B 20 21 22 23 24 25 26 27 28

1.2 (a) 32,768 (b) 67,108,864 (c) 6,871,947,674

1.3 (4310)5 = 4 * 5
3 + 3 * 52 + 1 * 51 = 58010

(198)12 = 1 * 12
2 + 9 * 121 + 8 * 120 = 26010


 
 
  (435)8
 =
 4
 *
 82
 +
 3
 *
 81
 +
 5
 *
 80
 =
 28510
 

 

 
 
  (345)6
 =
 3
 *
 62
 +
 4
 *
 61
 +
 5
 *
 60
 =
 13710
 

 
1.4 16-bit binary: 1111_1111_1111_1111

Decimal equivalent: 216 -1 = 65,53510
Hexadecimal equivalent: FFFF16

 

1.5 Let b = base

(a) 14/2 = (b + 4)/2 = 5, so b = 6

(b) 54/4 = (5*b + 4)/4 = b + 3, so 5 * b = 52 – 4, and b = 8

(c) (2 *b + 4) + (b + 7) = 4b, so b = 11

1.6 (x – 3)(x – 6) = x2 –(6 + 3)x + 6*3 = x2 -11x + 22

Therefore: 6 + 3 = b + 1m, so b = 8
Also, 6*3 = (18)10 = (22)8

 
1.7 64CD16 = 0110_0100_1100_11012 = 110_010_011_001 _101 = (62315 )8

1.8 (a) Results of repeated division by 2 (quotients are followed by remainders):

43110 = 215(1); 107(1); 53(1); 26(1); 13(0); 6(1) 3(0) 1(1)
Answer: 1111_10102 = FA16

(b) Results of repeated division by 16:

43110 = 26(15); 1(10) (Faster)
Answer: FA = 1111_1010

1.9 (a) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125

(b) 16.516 = 16 + 6 + 5*(.0615) = 22.3125

(c) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125

(d) DADA.B16 = 14*16

3 + 10*162 + 14*16 + 10 + 11/16 = 60,138.6875

Page 13

Digital
 Design
 With
 An
 Introduction
 to
 the
 Verilog
 HDL
 –
 Solution
 Manual.
 M.
 Mano.
 M.D.
 Ciletti,
 Copyright
 2012,
 
 
All
 rights
 reserved.
 

13
 

(d)
w x y z

Fsimplified

F


(e)

A B C D

Fsimplified = 0

F


(f)

w x y z

Fsimplified

F


 
2.7 (a)

A B C D

Fsimplified

F

Page 14

Digital
 Design
 With
 An
 Introduction
 to
 the
 Verilog
 HDL
 –
 Solution
 Manual.
 M.
 Mano.
 M.D.
 Ciletti,
 Copyright
 2012,
 
 
All
 rights
 reserved.
 

14
 

(b)
w x y z

Fsimplified

F


(c)

A B C D

Fsimplified

F


(d)

A B C D

Fsimplified

F

Page 25

Digital
 Design
 With
 An
 Introduction
 to
 the
 Verilog
 HDL
 –
 Solution
 Manual.
 M.
 Mano.
 M.D.
 Ciletti,
 Copyright
 2012,
 
 
All
 rights
 reserved.
 

25
 

2.28 (a) y = a(bcd)'e = a(b' + c' + d')e


a bcde

0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111

0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
0 1111

a bcde

1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111

1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111

y

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

y = a(b' + c' + d')e = ab’e + ac’e + ad’e
= Σ( 17, 19, 21, 23, 25, 27, 29)

y

0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0

(b) y1 = a ⊕ (c + d + e)= a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e'

y2 = b'(c + d + e)f = b'cf + b'df + b'ef

y1 = a (c + d + e) = a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e'

y2 = b'(c + d + e)f = b'cf + b'df + b'ef

a'-c---
001000 = 8
001001 = 9
001010 = 10
001011 = 11

001100 = 12
001101 = 13
001110 = 14
001111 = 15

011000 = 24
011001 = 25
011010 = 26
011011 = 27

011100 = 28
011101 = 29
011110 = 30
011111 = 31

a'--d--
000100 = 8
000101 = 9
000110 = 10
000111 = 11

001100 = 12
001101 = 13
001110 = 14
001111 = 15

010100 = 20
010101 = 21
010110 = 22
010111 = 23

011100 = 28
011101 = 29
011110 = 30
011111 = 31

a-c'd'e'-
100000 = 32
100001 = 33
110000 = 34
110001 = 35

a'---e-
000010 = 2
000011 = 3
000110 = 6
000111 = 7

001010 = 10
001011 = 11
001110 = 14
001111 = 15

010010 = 18
010011 = 19
010110 = 22
010111 = 23

011010 = 26
011001 = 27
011110 = 30
011111 = 31

-b' c--f

001001 = 9
001011 = 11
001101 = 13
001111 = 15
101001 = 41
101011 = 43
101101 = 45
101111 = 47

-b' -d-f

001001 = 9
001011 = 11
001101 = 13
001111 = 15
101001 = 41
101011 = 43
101101 = 45
101111 = 47

-b' --ef

000011 = 3
000111 = 7
001011 = 11
001111 = 15
100011 = 35
100111 = 39
101011 = 51
101111 = 55

Page 26

Digital
 Design
 With
 An
 Introduction
 to
 the
 Verilog
 HDL
 –
 Solution
 Manual.
 M.
 Mano.
 M.D.
 Ciletti,
 Copyright
 2012,
 
 
All
 rights
 reserved.
 

26
 

ab cdef

00 0000
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111

00 1000
00 1001
00 1010
00 1011
00 1100
00 1101
00 1110
00 1111

y1 y2

0 0
0 0
1 0
1 1
0 0
0 0
1 0
1 1

1 0
1 1
1 0
1 0
1 0
1 1
1 0
1 1

ab cdef

01 0000
01 0001
01 0010
01 0011
01 0100
01 0101
01 0110
01 0111

01 1000
01 1001
01 1010
01 1011
01 1100
01 1101
01 1110
01 1111

y1 y2

0 0
0 0
1 0
1 0
0 0
0 0
1 0
1 0

1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0

ab cdef

10 0000
10 0001
10 0010
10 0011
10 0100
10 0101
10 0110
10 0111

10 1000
10 1001
10 1010
10 1011
10 1100
10 1101
10 1110
10 1111

y1 y2

1 0
1 0
1 0
1 1
0 0
0 0
0 0
0 1

0 0
0 1
0 0
0 1
0 0
0 1
0 0
0 1

ab cdef

11 0000
11 0001
11 0010
11 0011
11 0100
11 0101
11 0110
11 0111

11 1000
11 1001
11 1010
11 1011
11 1100
11 1101
11 1110
11 1111

y1 y2

0 0
0 0
0 0
0 1
0 0
0 0
0 0
0 1

0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0

y1 = ! (2, 3, 6, 7, 8, 9, 10 ,11, 12, 13, 14, 15, 18, 19, 22, 23, 24, 25, 26, 27, 28,
29, 30, 31, 32, 33, 34, 35 )

y2 = ! (3, 7, 9, 13, 15, 35, 39, 41, 43, 45, 47, 51, 55)

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