Title LOGIC DESIGN 927.9 KB 227
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Digital Logic Design Page 2

Background and Acknowledgements

This material has been developed for the first course in Digital Logic Design. The content is derived from
the author’s educational, technical and management experiences, in-addition to teaching experience.
Many other sources, including the following specific sources, have also informed by the content and
format of the following material:

 Katz, R. Contemporary Logic Design. (2005) Pearson.
 Wakerly, I. Digital Design. (2006) Prentice Hall.
 Sandige, R. Digital Design Essentials. (2002) Prentice Hall.
 Nilsson, J. Electrical Circuits. (2004) Pearson.

I would like to give special thanks to my students and colleagues for their valued contributions in making
this material a more effective learning tool.

I invite the reader to forward any corrections, additional topics, examples and problems to me for future

Thanks,

www.EngrCS.com

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 Mixed-type Synchronous Finite State Machine
Some outputs are Mealy-type and others are Moore-type.

 Analyzing Synchronous Systems (General)
There are five steps in analysis of this type of circuit:

1) Assign a present state variable to each flip flop in the synchronous system.

Yi represents flip-flop outputs for i = 1, 2, 3, …

2) Write the excitation-input equation for each of the flip-flops and the external-output
(Moore and/or mealy equations). After completing this step, Di, Ji Ki, Ti should be
defined where i=1, 2, 3 … {# of flip-flops used}.

3) Substitute the excitation input equation into the characteristic equations of the flip-
flops to obtain the “next state” equations.
For D flip-flops  Yi+ = Di for i=1, 2, 3, …
For J-K flip-flops  Yi+ = Ji.Yi’ + Ki’.Yi for i=1, 2, 3, …
For T flip-flops  Yi+ = Ti <XOR> Yi for i=1, 2, 3, …

4) Obtain a PS/NS table or a composite K-map using the next state and external-out
(Mealy and/or Moore) equations. Separate K-maps can be used for the external

Excitation
Forming Logic

(Combinational)

Flip Flops

Input
Output

Clock System

Clock

External
Inputs (Xs)

Mealy
External Output
Zs(Ys, Xs) Ys

Excitation
input

Feedback

Mealy Output
Forming Logic

(Combinational)

Moore Output
Forming Logic

(Combinational)

Moore
External Output
Zs(Ys)

Excitation
Forming Logic

(Combinational)

Flip Flops

Input
Output

Clock System

Clock

External
Inputs (Xs)

Mealy
External Output
Zs(Ys, Xs) Ys

Excitation
input

Feedback

Mealy Output
Forming Logic

(Combinational)

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outputs if desired.

5) Use the PS/NS table or the composite K-map to obtain a state diagram, ASM chart or
timing diagram to show the behavior of the circuit.

 Apply the five step analysis technique to the following circuit:

Note: This is a Mealy-type machine since the output depends on external input and flip-flop outputs.

1) Assign a present state variable to each flip flop in the synchronous system.

Yi representing flip-flop outputs for i = 1, 2, 3, …
Solution: Refer to the schematics

2) Write the excitation-input equation for the flip-flops and the equation for the external-output
(Moore and/or mealy equations). After this step is completed, the values of Di, Z should be
defined for all flip-flops.

Solutions:
D1 = X’.Y1’.Y2
D2 = Y1’.Y2 + X
Z = Y1.Y2.X

3) Substitute the excitation-input equation into the characteristic equations for the flip-flops to
obtain the “next state” equations.

D flip-flops  Yi+ = Di for i=1, 2, 3, …

Solutions:
Y1+ = D1 = X’.Y1’.Y2
Y2+ = D2 = Y1’.Y2 + X

4) Obtain a PS/NS table or a composite K-map using the next state and external-output (Mealy
and/or Moore) equations. Separate K-maps can be used for the external outputs if desired.
Solutions:

X

D1

C1

D2

C2 System

Clock

Q1’

Q2

Q2’

Q1
Z Y1

Y2

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9.9. Problems

Refer to www.EngrCS.com or online course page for complete solved and unsolved problem set.

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Digital Logic Design Page 227